Silicon based technology has advanced in the past two decades as Moore's law predicted. A large number of computing cores, complex memory subsystems, and I/O devices are now packed onto modern VLSI chips such that the computational power per unit area has grown tremendously. To deliver petascale performance today, huge amounts of resources are being deployed via interconnected computing units, while programming languages and paradigms are being pushed beyond their initial designs to explore maximal parallel efficiency. As a consequence, work on application enablement has become an extremely challenging task. Furthermore, in the foreseeable future, exa- and higher scale computing systems are expected to incorporate even more massive numbers of multi-core processors and accelerators, such as the Graphics Processing Units (GPU) and co-processors Xeon Phi, which will pose critical challenges for enabling, optimizing and tuning applications on these systems. Therefore, there will be an increasingly urgent need to have efficient performance modeling, tuning, and enablement tools that address such challenges in extreme scale computing. 

The goal of this workshop is to promote community-wide discussion identifying the methodologies, analysis, and software tools, which can enable effective and scalable performance evaluation for extreme scale computing systems. We seek submissions of papers that invent new techniques, introduce new methodologies, propose new research directions and discuss approaches for unsolved issues.  In particular, contributions presenting novel, original work in all areas of GPU from hardware abstractions to specific applications in clouds are welcome.

The topics of this workshop are related to methodological aspects as well as practical of the application enablement in extreme scale computing. Topics of interest include (but are not limited to)

• Performance modeling for all aspects of extreme scale systems, e.g., cores, memory, interconnect and I/O, etc.
• Algorithms for self-tuning and -optimization of applications in extreme scale computing
• Profiling and debugging tools for applications in extreme scale computing
• Performance, tracing and simulation tools with extreme scalability
• Methodologies and tools for extreme scale performance evaluation, and verification
• Power efficiency
• Empirical and deployment studies of extreme scale performance tools: challenges, techniques and lessons
• Researches on acclerator-based high performance computing, such as:
• Accelerator architecture
• Benchmarking/measurements/scalability
• Compilers and operating systems
• Sharing, scheduling, and migration
• Fault tolerant computing
• Debugging and profiling
• Hybrid system for accelerators with OpenMP, Pthread, and MPI

Important Dates

Submission Deadline:	August 15, 2013
Author Notification:	September 1, 2013
Final Manuscript Due:	September 15, 2013
Registration Due:	September 15, 2013
Workshop Date:	November 13-15, 2013

Submission Instructions

Prospective authors are invited to submit manuscripts reporting original unpublished research and recent related developments. The length of the papers should not exceed 6 pages + 2 pages for overlength charges (IEEE Computer Society Proceedings Manuscripts style: two columns, single-spaced, 10-point font), including figures and references. You can confirm the IEEE Computer Society Proceedings Author Guidelines.

Distinguished papers, after further revisions, will be published in 10 SCI and EI indexed special issues, which will be shared by the IEEE HPCC 2013 conference and its symposiums and workshops. (Details)

At least one of the authors of any accepted paper is requested to register the paper.

Submission Link: https://www.easychair.org/conferences/?conf=escape2013

Workshop Co-Chairs

Workshop Committee

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