Hsinchu, Taiwan, R.O.C., December 2-4, 1998
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11TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS (ISSS) Hsinchu, Taiwan, R.O.C., December 2-4, 1998 |
| SLIDES |
| 1.1 | A Uniform Optimization Technique for Offset Assignment Problems Rainer Leupers, Fabian David; Dept. of Computer Science,Univ. of Dortmund |
| 2.2 | Intellectual Property Re-use in Embedded System Co-design: an Indutrial Case Study E. Filippi, L. Lavagno, L. Licciardi, A. Montanaro, M. Paolini, R. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi; CSELT, Italy. Dipartimento di Elettronica, Politecnico di Torino, Italy. Univ. of CA. at Berkeley, USA. |
| 3.1 | Application-Specific Heterogenous Multiprocessor Synthesis Using Differential-Evolution A. Rae, S. Parameswaran; Dept. of Computer Science and Electrical Eng. Univ. of Qu`ensland, Australia. |
| 3.2 | Proposal for unified system design meta flow in task-level and instruction-level design technology research for multi-media applications F. Catthoor, D. Verkest, E. Brockmeyer; IMEC, VSDM Division, Katholieke Univ. Leuven |
| 3.3 | Data-path Synthesis of VLIW Video Signal Processors Z. Wu, W. Wolf; Dept. of Electrical Eng., Princeton Univ., U.S.A. |
| 4.1 | Synchronization Detection for Multi-Process Hierarchical Synthesis O Bringmann, W. Rosenstiel, D. Reichardt; FZI and Univ. of Tubingen, Germany |
| 4.2 | Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign P. V. Knudsen and J. Madsen; Dept. of Information Technology, Technical Univ. of Denmark, Denmark |
| 5.2 | Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Alloation I.-J. Huang, P.-H. Xie; Institute of Computer and Information Eng., NSYSU Kaohsiung, Taiwan, R.O.C. |
| 5.3 | Memory Efficient Software Synthesis from Dataflow Graph W. Sung, Junedong Kim, Soonhoi Ha; Dept. of Computer Eng., Seoul National University, Korea |
| 6.1 | A Tool Partitioning and Pipelined Scheduling of Hardware-Software Systems Karam S. Chatha and Ranga Vemuri; Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati |
| 6.3 | Fine-Grain, Incremental Rescheduling Via Architectural Retiming Retiming; S. Hassoun; Dept. of Electrical Eng. and Computer Science, Tufts University |
| P1 | HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation R. Leupers; Dept. of Computer Science, Univ. of Dortmund |
| P2 | False Path Analysis based on a Hierarchical Control Representation A. A. Kountouris and C. Wolinski; IRISA - Institut de Recherche en Informatique et Systemes Aleatoires |
| P3 | Resource constrained Modulo Scheduling with Global Resource Sharing C. Jaeschke, R. Laur; Univ. of Bremen, Dept. 1, Institute of Electromagnetic Theory and Micro., Bremen/Germany. |