Ching-Te Chiu
Publications
1. C.T.Chiu, K.J.R. Liu, ¡§Real-Time Parallel
and Fully-Pipelined Two-Dimensional DCT Lattice Structures with Application to
HDTV Systems,¡¨ IEEE Trans. on Circuits
and Systems for Video Technology, Vol. 2, No. 1, pp. 25-37, March 1992.
(SCI/SSCI=5/208, Number of citation=49)
2.
K.J.R., Liu, S.F. Hsieh, K.Yao, and C.T.Chiu, ¡§Dynamic Range, Stability, and
Fault-tolerant Capability of Finite-precision QRD RLS Systolic Algorithm, ¡¨ IEEE Trans. on Circuit and Systems, vol.
38, No. 6, pp. 625-636, June, 1991.(SCI/SSCI=5/208, Number of citation = 12)
3.
K.J.R. Liu, and C.T.Chiu, ¡§Unified
Parallel Lattice Structures for Time-Recursive Discrete Cosine/Sine/Hartley
Transforms, ¡¨ IEEE Trans. on Signal
Processing, Vol. 41, No. 3, pp. 1357-1377, March 1993.(SCI/SSCI=34/208,
Number of citation=69)
4.
K.J.R. Liu, C.T.Chiu, R. K. Kolagotla, and J. F. JáJá,
¡§Optimal Unified Architectures for the Real-Time Computation of Time-Recursive
Discrete Sinusoidal Transforms,¡¨ IEEE Trans.
on Circuits and Systems for Video Technology , April,
1994.(SCI/SSCI=5/208, Number of
citation=58)
5.
M.S. Kao, J.M. Wu, C.H. Lin, F.T. Chen, C.T.Chiu,
S.H. Hsu, ¡§A 10Gb/s CML I/O Circuit
for Backplane Interconnection in
6.
Y.H. Hsu, C.T.Chiu, Y.S. Hsu, etc., ¡§A
Quarter-Rate 2.56/3.2Gbps 16/20:1 SERDES Interface in 0.18£gm CMOS Technology,¡¨ International Journal of Electrical
Engineering, vol. 16, No. 1, pp. 39-49, Jan. 2009.
7.
J.S. Tsai, C.H. Lin and C.T.Chiu,
¡§Switching Bilateral Filter with a Texture/Noise Detector for Universal Noise
Removal,¡¨ IEEE Trans. On Image Processing,
vol. 19, No. 9, pp. 2307-2320, 2010.
8.
Ching-Te Chiu, Tsun-Hsien Wang,
Wei-Ming Ke ,Chen-Yu Chuang, Jhih-Rong
Chen, Rong Yang and Ren-Song Tsay,
¡§A 100MHZ Real-Time Tone Mapping Processor with Integrated Photographic and
Gradient Compression in 0.13 £gm Technology,¡¨ Journal of Signal Processing, VLSI Systems,
17 June 2010. http://www.springerlink.com/content/01637303ju2r6853/.
9.
W.M. Ke and C.T.Chiu,
¡§BiTA/SWCE: Image Enhancement with Bilateral Tone
Adjustment and Saliency Weighted Contrast Enhancement,¡¨ IEEE Trans. on Circuits and Systems for Video Technology, vol. 21,
No. 3, pp. 360-364, 2011.
10. C.R.Chen, W.S.Wong
and C.T.Chiu, ¡§A 0.64 mm^2 Real-Time Cascade
Face Detection Design Based on Reduced Two-Field Extraction,¡¨ IEEE Trans. on Very Large Scale Integration Systems, vol. 19, No. 11, pp.
1937-1948, 2011.
11. C.T.Chiu, T.H. Wang, R.J. Wang, and J.S.
Huang, ¡§An 8¡Ñ8 20 Gbps Reconfigurable Load Balanced TDMSwitch IC for High-Speed Networking¡¨ Journal of Signal Processing,
VLSI Systems. Volume 66, No. 1 57-73, 2012. http://www.springerlink.com/content/00540883K3072282.
12. Wei-Yu Tsai, Ching-Te Chiu,
Jen-Ming Wu, Shawn S.H. Hsu, and Yar-Sun Hsu, ¡§A
Novel Low Gate-Count Pipeline Topology with Multiplexer-Flip-Flops for Serial
Link,¡¨ IEEE Transactions on Circuits and
Systems I, Issue 99, pp. 1-11, Aug. 2012.
13. Ching-Te Chiu, Yu-Hao Hsu, Wei-Chih Lai, Jen-Ming Wu, Shawn S.H. Hsu, Yang-Syu Lin, Fan-Ta Chen, Min-Shen Kao, and Yar-Sun
Hsu, ¡§A Low Propagation Delay Load Balanced 4x4 Switch Fabric IC in 0.13um CMOS
Technology,¡¨ IEEE Transactions on Very
Large Scale Integrated Systems, Vol. 2, No. 8, pp. 1481-1495, August 2013.
14. Ching-Te Chiu, Wen-Chih Haung, Chih-Hsing
Lin, Wei-Chih Lai, and Ying-Fang Tsao, ¡§Embedded
Transition Inversion Coding with Low Switching Activity for Serial Links,¡¨ IEEE Transactions on Very Large Scale
Integrated Systems, Vol. 21, No. 10, pp. 1797-1810, October 2013.
15. Wei-Chih
Lai and Ching-Te Chiu, ¡§Data Center
Switch for Load Balanced Fat-Trees,¡¨ Journal of Signal Processing, VLSI Systems, Vol. 71, Issue 3, pp. 173-187, June 2013.
16. F.T. Chen , M.S. Kao, Y.H. Hsu,
J.M. Wu,, C.T.Chiu, and , S.H. Hsu, ¡§A 10Gb/s
Low Jitter Single-Loop Clock and
Data Recovery Circuit with Rotational Phase Frequency Detector,¡¨ IEEE
Trans. on Circuits and Systems I, accepted 2014.
17. W.C. Wu, T.H. Wang and .C.T. Chiu,
¡§Contour Extraction and Scaling for Single Image Super Resolution,¡¨ Journal of Signal Processing,
VLSI Systems, accepted 2014.
18. Po-Chien
Chiu, Y.S. Hsu, and C.T. Chiu, ¡§Cluster Ring Controller Area Network for
Enhanced Transmission and Fault-Tolerance in Vehicle Networks,¡¨ International
Journal of Education and Research, Sept., 2014.
19. Po-Chien
Chiu, Y.S. Hsu, and C.T. Chiu, ¡§Analysis of Cluster Ring Controller/Area
Network for Enhanced Transmission and Fault-Tolerance Capability on Vehicle
Networks,¡¨ book chapter, pp. 101-110, Advanced Microsystems for Automotive
Applications, Smart Systems for safe, clean, and automated vehicles, Springer.
Conferences
1. C.T. Chiu, and K.J.R. Liu, ¡§Parallel Implementation of Transformed-Based DCT Filter Bank for Video Communications,¡¨ Proceeding of IEEE International Conference on Consumer Electronics, June 1994.
2. K.J.R. Liu and C.T. Chiu, ¡§Unified VLSI Lattice Architectures for Discrete Sinusoidal Transforms,¡¨ Proceeding of the 35th Midwest Conference, Washington, DC, Aug. 1992.
3. C.T. Chiu, R. Kolagotla, K.J.R. Liu, and J.F. JáJá, ¡§VLSI implementation of Real Time Parallel DCT/DST Lattice Structures,¡¨ Proceeding of IEEE workshop on VLSI Signal Processing, pp. 101-110, 1993.
4. K.J.R. Liu, C.T. Chiu, R. K. Kolagotla and J. F. JáJá, ¡§Optimal Unified IIR Architectures for Time-Recursive Discrete Sinusoidal Transforms,¡¨ Proceeding of IEEE ICASSP-93, MN, 1993
5. C.T. Chiu, and K.J.R. Liu, ¡§Real-Time Recursive Two-Dimensional DCT for HDTV Systems,¡¨ IEEE ICASSP Proc., pp. III 205-208, March 1992.
6. C.T. Chiu, and K.J.R. Liu, ¡§Theoretical Analysis for Recursive Computation of Discrete Sinusoidal Transforms,¡¨ IEEE Ten'con 94, Singapore, Aug., 1994.
7. C.T. Chiu, and K.J.R. Liu, ¡§Unified Lattice Architectures for Time-Recursive Discrete Sinusoidal Transforms with Applications to Real-Time Video Communications,¡¨ Advances in VLSI Signal Processing, 1994
8. C.-T. Chiu, J.M. Wu, C.C. Chang, etc. ¡§ A 20Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications,¡¨ IEEE IWSOC 2005, Banff Canada, July 2005.(NSC93-2752-E-007-002-PAE).
9. M.S. Kao, C.H. Jen, C.T.Chiu, etc., ¡§A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18£gm CMOS Technology,¡¨ IEEE ISOCC 2005, Washington D.C., USA Sep 2005.(NSC93-2752-E-007-002-PAE)
10. C.T.Chiu, Z.S. Hsiao, C.H. Jen, ¡§A 3.2Gb/s 20:1 CML Transmitter in 0.18 CMOS Technology,¡¦¡¦ VLSI Design/CAD, 2005, Hau-Lien, Taiwan, Aug, 2005.(NSC93-2752-E-007-002-PAE)
11. C.Y. Tu, C.S. Chang, D.S. Lee, and C.T.Chiu, ¡§Design a Simple and High Performance Switch Using a Two-stage Architecture,¡¨ IEEE Globecom 2005, St. Louis, Missouri, USA, Dec., 2005.(NSC93-2752-E-007-002-PAE)
12.
D. Svensson
and C.T. Chiu, ¡§Robust Interconnect Design in Mixed Clock systems,¡¨ ECS 2005, Bratislava, Slovakia, Sep,
2005.(NSC94-2215-E-007-016)
13. C.H. Hsiao, M. S. Kao, C. H. Jen, Y. H. Hsu, P. L. Yang, C.T. Chiu, J. M. Wu, S. H. Hsu, Y. S. Hsu, ¡§A 3.2Gb/s CML Transmitter with 20:1 Multiplexer in 0.18Um CMOS technology,¡¨ 13th International Conference Mixed Design of Integrated Circuits and Systems MIXDES, Poland, June 22~24, 2006. (NSC93-2752-E-007-002-PAE)
14.
H.C. Tzeng, C.T. Chiu, ¡§A Flexible Cross Connect LCAS for
Bandwidth Maximization in
15. Y.Y. Hsu, H.Y. Lin, F.T. Chen, H.Y. Lin, C.T.Chiu, J.M. Wu, S.H. Hsu, ¡§A Low Power 2.56/3.2 Gbps Dual Mode 16/20:1 Serial-Link Transmitter,¡¨ VLSI Design/CAD 2006, pp. 634-637, Hau-Lien, Taiwan, Aug, 2006. (NSC93-2752-E-007-002-PAE)
16.
Hou-Cheng
Tzeng, C.T.Chiu, ¡§A
Flexible Cross Connect LCAS for Bandwidth Maximization in
17. M.C. Du, C.T. Chiu, ¡§Real-Time User-select Video Streaming on a P2P Network,¡¨ IEEE 13th International Conference on Systems, Signals, and Image Processing, Hungary, Sep., 2006.(NSC94-2215-E-007-016)
18. Y.Y. Hsu, M.S. Kao, H.C.Tzeng, C.T.Chiu, J.M. Wu, and S.H.Hsu, ¡§A 20Gbps scalable load balanced Birkhoff-von Neumann symmetric TDM switch IC with SERDES interfaces,¡¨ IEEE proceedings of the 12th Asia and South Pacific Design Automation Conference, pp. 23-26, Yokohama, Japan, 2007. (NSC-95-2752-E-007-002-PAE).
19. C.H. Lin and C.T.Chiu, ¡§A 80-400MHz Wide Range Low Jitter DLL-Based Frequency Multiplier Using PMOS Active Load for Communication Applications,¡¨ IEEE International Symposium on Circuits and Systems, pp. 3888-3891, New Orleans, USA, May 27-30, 2007.(NSC94-2215-E-007-016)
20. C.T. Chiu, Y.H. Hsu, M.S. Kao,H.C. Tzeng, etc., ¡§A Scalable Load Balanced Birkhoff-Von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications,¡¨ IEEE International Symposium on Circuits and Systems, pp. 2754-2757, New Orleans, USA, May 27-30, 2007. (NSC93-2752-E-007-002-PAE)
21. T.S. Wang, and C.T. Chiu, ¡§Low Power Design of High Performance Memory Access Architecture for HDTV Decoder¡¨, IEEE International Conference on Multimedia and Expo, pp. 699-702, Beijing, China, July 2-6, 2007. ( NSC 95-2220-E-007-033).
22. C.T. Chiu, J.M. Wu, S.H. Hsu ,etc. , ¡§A Quarter rate 2.56/3.2 Gbps 16/20:1 SERDES Interface in 0.18ƒÝm CMOS technology,¡¨ VLSI Design/CAD 2007, pp. 634-637, Hau-Lien, Taiwan, Aug, 2007. (NSC94-2752-E-007-002-PAE)
23. T.H. Wang, W.M. Ke, D.C. Zwao , F.C. Chen, and C.T. Chiu, ¡§Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video,¡¨ VLSI Design/CAD 2007, Hau-Lien, Taiwan, Aug , 2007. (NSC 95-2220-E-007-033).
24. T.H. Wang, W.S. Wong, F.C. Chen, and C.T. Chiu,
¡§Block-Based Gradient Domain High Dynamic Range Compression Design for
Real-Time Implementations,¡¨ VLSI
Design/CAD 2007, Hau-Lien, Taiwan, Aug, 2007. ( NSC 95-2220-E-007-033).
25. T.H. Wang, W.M. Ke, D.C. Zwao, F.C. Chen, and C.T. Chiu, ¡§Design and Implementation of a
Real-Time Global Tone Mapping Processor for High Dynamic Range Video,¡¨ IEEE International Conference on Image Processing,
VI, pp.209-212, San Antonio, TX, USA, Sep. 16-19, 2007. (NSC
95-2220-E-007-033).
26. T.H. Wang, W.S. Wong, F.C. Chen, and C.T. Chiu, ¡§Block-Based Gradient Domain High
Dynamic Range Compression Design for Real-Time Implementations,¡¨ IEEE International Conference on Image
Processing, San Antonio, TX, torao, USA, Sep.
16-19, 2007. ( NSC 95-2220-E-007-033).
27. H.J. Hsu, C.T. Chiu, Y.S. Hsu, ¡§Design of Ultra Low Power CML MUXs and Lacthes with Forward Body Bias,¡¨ IEEE20th International SOC Conference, pp. 141-144, Hsinchu, Taiwan, Sept. 26-29, 2007. (NSC93-2752-E-007-002-PAE).
28.
Y.H. Hsu, M.M. Lu, P.L. Yang, C.T.
Chiu, etc., ¡§A 28Gbps 4¡Ñ4 Switch with Low Jitter SerDes
using Area-Saving RF Model in 0.13µm CMOS Technology¡¨, IEEE International Symposium on Circuits and Systems ,pp.3086-3089,
ISCAS 2008, May Seattle, USA, 2008.
29.
C.T. Chiu, T.H. Wang, etc., ¡§Design Optimization of A Global/Local Tone
Mapping Processor on ARM SOX Platform for Real-time High Dynamic Range Video,¡¨ ICIP 2008. IEEE International Conference on
Image Processing, 2008, pp. 1400-1403, San Diego, USA. Oct. 12~16, 2008.
30.
C.T. Chiu, T.H. Wang, etc., ¡§A 100MHz Real-time Tone Mapping Processor
with Integrated Photographic and Gradient Compression in 0.13 £gm Technology,¡¨ SiPS
2008. IEEE Workshop on Signal Processing Systems, pp. 25-30, Washington
D.C., USA. Oct. 7~10, 2008.
31.
C.H. Lin and C.T.
Chiu, ¡§A 2.64GHz Wide Range Low power DLL-Based
Frequency Multiplier with CML Circuits using Adaptive Body Bias,¡¨
IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2008
32.
C.H. Lin and C.T. Chiu, ¡§A 2.64GHz Wide Range DLL-Based Multi-Phase Clock
Generator with Low Power CML Circuits using Adaptive Body Bias,¡¨ VLSI Design/CAD 2008, S10-2, Ken-ting,
Taiwan, Aug, 2008.
33.
C.T.Chiu, T. C. Hsieh, W.M. Ke
and T.H. Wang, ¡§A Perception Based High Dynamic
Range Image Encoding with Discrete Wavelet Transform,¡¨ VLSI Design/CAD 2008, S6-4, Ken-ting, Taiwan, Aug, 2008.
34.
T.H. Wang, C.T. Chiu, R.S. Tsay, etc. , ¡§Design Optimization of A Global/Local Tone Mapping Processor
on ARM SOX Platform for Real-time High Dynamic Range Video,¡¨ VLSI Design/CAD 2008, P1-17, Ken-ting,
Taiwan, Aug, 2008.
35.
W.S. Wong, C.R. Chen, and C.T. Chiu, ¡§A 100MHz Hardware-Efficient
Boost Cascaded Face Detection Design,¡¨ ICIP
2009, IEEE International Conference on Image Processing, 2009. (NCS97-2220-E-007-021)
36.
W.M., Ke, T.H. Wang and C.T. Chiu,
¡§Hardware-Efficient Virtual High Dynamic Range Image Reproduction,¡¨ ICIP 2009, IEEE International Conference on Image Processing,
2009.
(NCS97-2220-E-007-021)
37.
Wei-Su Wong, Chih-Rung
Chen, and Ching-Te Chiu, ¡§A Low Cost and High Speed Boost Cascaded Face
Detection Design and Implementation,¡¨ VLSI Design/CAD,
17-1, Ken-ting, Taiwan, August 2009. (NCS97-2220-E-007-021)
38.
Wei-Ming Ke, Tsun-Hsien Wang, and
Ching-Te Chiu, ¡§Hardware-Efficient
Virtual High Dynamic Range Image Reproduction,¡¨ VLSI Design/CAD, 17-1, Ken-ting, Taiwan, August 2009.
(NCS97-2220-E-007-021)
39.
Kun-Che Tsai, Jia-Shiuan
Tsai, Tsun-Hsien Wang, and Ching-Te Chiu, ¡§A SOC Platform-based Adaptive Bilateral Filter Design for Real-time
Applications,¡¨ VLSI Design/CAD,
17-1, Ken-ting, Taiwan, August 2009. (NCS97-2220-E-007-021)
40.
C.H. Lin, Jia-Shiuan Tsai and C.T. Chiu, ¡§Switching
Bilateral Filter with a Texture/Noise Detector for Universal Noise Removal,¡¨
IEEE ICASSP 2010, Dallas, TX, USA.
41.
Y.H. Hsu, Y.C.Lin,
C.T. Chiu, etc., ¡§A 32Gbps Low Propagation Delay 4¡Ñ4 Switch IC for Feedback-Based
System in 0.13£gm CMOS Technology,¡¨ IEEE
ICAS 2010, Paris, France.
42.
C.H. Lin, C.T. Chiu, etc., ¡§A Packet-based Emulating Platform with Serializer/Deserializer Interface
for Heterogeneous IP Verification,¡¨ IEEE
ICAS 2010, Paris, France.
43.
Wei-Yu Tsai, Ching-Te Chiu,
etc., ¡§A Novel MUX-FF Circuit for
Low Power and High Speed Serial Link Interfaces,¡¨ IEEE ICAS 2010, Paris, France.
44.
Wei-Ming Ke,
and Ching-Te Chiu, ¡§Hardware-Efficient
Image Enhancement with Bilateral Tone adjustment,¡¨ IEEE ICAS 2010, Paris, France.
45.
Po-Ting Yeh,
Ching-Te Chiu, Cyuan-Jhe Wu, ¡§IBARP-An Improved Balanced Adaptive Routing Protocol for
Efficient Hard Realization,¡¨ SiPS 2010. IEEE Workshop on Signal Processing Systems, Cupertino, USA.
46.
C.H. Lin, Jia-Shiuan Tsai and C.T. Chiu, ¡§Switching
Bilateral Filter with a Texture/Noise Detector for Universal Noise Removal,¡¨
VLSI/CAD 2010, Kaohsiung, Taiwan.
47.
Y.H. Hsu, Y.C.Lin,
C.T. Chiu, etc., ¡§A 32Gbps Low Propagation Delay 4¡Ñ4 Switch IC for Feedback-Based
System in 0.13£gm CMOS Technology,¡¨ VLSI/CAD
2010,
Kaohsiung, Taiwan.
48.
C.H. Lin, C.T. Chiu, etc., ¡§A Packet-based Emulating Platform with Serializer/Deserializer Interface
for Heterogeneous IP Verification,¡¨ VLSI/CAD 2010, Kaohsiung, Taiwan.
49.
Wei-Ming Ke,
and Ching-Te Chiu, ¡§Hardware-Efficient
Image Enhancement with Bilateral Tone adjustment,¡¨ CVGIP2010, Kaohsiung, Taiwan.
50.
Yung-Chang Chang, Ching-Te
Chiu, ¡§On the Design and Analysis of Fault Tolerance NoC
Architecture Using Spare Routers,¡¨ ASP-DAC
2011.
51.
Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung
Hsu, Fan-Ta Chen, Min-Sheng Kao, Wei-Chih Lai, YarSun Hsu, ¡§A 32Gbps Low Propagation Delay 4x4 Switch IC
for Feedback-Based System in 0.13um CMOS Technology,¡¨ ASP-DAC 2011.
52.
Chih-Rung Chen, and Ching-Te Chiu, "Curve-Based and Image-based JND
Contrast Analysis for Inverse Tone Mapping Operators,¡¨ IEEE International Conference on Image Processing, Sept. 2011, pp.
353-356.
53.
Tsun-Hsien Wang, and Ching-Te Chiu, ¡§Low
Visual Difference Virtual High Dynamic Range Image Synthesizer from A Single
Legacy Image,¡¨ IEEE International Conference
on Image Processing, Sept. 2011, pp. 2313-2316.
54.
Ching-Te Chiu, and Cyuan-Jhe Wu, ¡§Texture Classification Based Low Order Local Binary Pattern for Face
Recognition,¡¨ IEEE International Conference
on Image Processing, Sept. 2011, pp. 3078-3081.
55.
Ruei-Jiun Wang, and Ching-Te
Chiu, ¡§Saliency Prediction using Scene Motion for JND
based Video Compression,¡¨ IEEE Workshop
on Signal Processing Systems, Oct., 2011, pp. 73-77.
56.
Wen-Chih
Huang, Chih-Hsing Lin and Ching-Te Chiu, ¡§Embedded
Transition Inversion Coding for Low Power Serial Link,¡¨ IEEE Workshop on Signal Processing Systems, Oct., 2011, pp.
102-105.
57.
Chih-Rung Chen, Ching-Te
Chiu and Yung-Chang Chang, ¡§Inverse Tone Mapping Operators
Evaluation Using Blind Image Quality Assessment,¡¨ Asia-Pacific Signal and Information Processing Association Annual
Summit and Conference, APSIPA Oct. 2011.
58.
Sih-Kai Li, Jen-Shun Yang, Ching-Te Chiu, Po-Ting Yeh,
and Jenq-Neng Hwang, ¡§Handover Delay Reduction and
Buffer-Based Data Recovery Scheme for Inter Multicast Broadcast Service Zone,¡¨ IEEE Globecom,
Dec., 2011.
59.
Jen-Chieh Chih,
Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, and Yar-Sun Hsu, ¡§Piecewise-Linear Phase Frequency Detector for
Fast-Lock Phase-Locked Loops,¡¨ IEEE International Midwest Symposium on
Circuits and Systems, Korea, 2011.
60.
Wei-Chih Lai and Ching-Te Chiu, ¡§ A 5.8Gbps Uniform
Mapping Data Center Switch,¡¨ IEEE ICASSP Kyoto, Japan, March 2012.
61.
Wei-Yu Tsai, Ching-Te Chiu,
Jen-Ming Wu, Shawn S.H. Hsu, and Yar-Sun Hsu, ¡§A
Novel Low Gate-Count Serializer Topology with
Multiplexer-Flip-Flops,¡¨ IEEE ISCAS,
Korea, 2012.
62.
Po-Ting Yeh and Ching-Te Chiu,¡§A Fault-Tolerant Multicast
Routing for Fat-Tree Based Data Center Networks¡¨ ICC
2012 Workshop, IEEE International Conference on
Communications Workshop , 2012
63.
T.J. Wu,
Ching-Te Chiu, and Li Lin, ¡§Texture Based Low Order
Descriptor for Pattern Recognition, ¡§ CVGIP, Taiwan 2012.
64.
Yung-Chang Chang, and Ching-Te
Chiu, ¡§A Study of NoC Topologies and Switching
Arbitration Mechanisms, ¡§2012 The 2nd
International Workshop on Embedded Multi-Core computing and Applications (EMCA
2012).
65.
Ruei-Jiun, Ching-Te Chiu, and Li Lin, ¡§Scene Motion
based Saliency Prediction for JND based Video Compression, ¡§ CVGIP, Taiwan, Aug. 2012.
66.
Wei-Chih Liu, Yar-Sun Hsu, and
Ching-Te Chiu, ¡§Cluster-Based
CAN with Enhanced Transmission Capability for Vehicle Networks,¡¨ ICCVE, PeiJing, Dec. 2012.
67.
I-Cheng Tsai
and Ching-Te Chiu, ¡§Depth-based
Posture Recognition by Radar and Vision Fusion for Real-Time Applications,¡¨ IEEE ICASSP, pp. 2702-2706, Vancouver, Canada, 2013.
68.
Wei-Chen
Wu, Tsun-Hsien Wang, and Ching-Te Chiu, ¡§Edge Curve Scaling and Smoothing with Cubic Spline
Interpolation,¡¨ IEEE
International Conference on Image Processing, pp. 859-862, Melbourne, Australia,
Sept., 2013.
69.
Wei-Chen
Wu, Tsun-Hsien Wang, and Ching-Te Chiu, ¡§Edge Curve Scaling and Smoothing with Cubic Spline
Interpolation for Image Upscaling,¡¨ IEEE Workshop on Signal Processing Systems, Oct. Taipei, Taiwan., 2013.
70.
Yin Mei, Ching Te Chiu, and Yar Sun
Hsu, ¡§SQMV BASED VISION AND RADAR FUSION VEHICLE DETECTION
SYSTEM¡¨ CVGIP, Taiwan, 2013.
71.
Ying-Fang
Tsao, Wen-Te Liu, and Ching-Te Chiu, ¡§Human
Gait Analysis by using body segmentation and Center of Gravity,¡¨ APSIPA, 2013,
Oct., Kaohsiung, Taiwan.
72.
Li Lin and Ching-Te Chiu, ¡§Low Cost Illumination Invariant Face
Recognition by Down-Up Sampling Self Quotient Image,¡¨ APSIPA, 2013, Oct.,
Kaohsiung, Taiwan.
73.
Yao Tsung Yang and Ching-Te
Chiu, ¡§BOOSTED MULTI-CLASS OBJECT DETECTION WITH PARALLEL HARDWARE IMPLEMENTATION
FOR REAL-TIME APPLICATIONS,¡¨ ICASSP 2014, May, Florence Italy.
74.
.Y.C. Chang, L.R. Haung,
H.C. Liu, C.J. Yang, C.T. Chiu ¡§Assessing
Automotive Functional Safety Microprocessor with ISO 26262 Hardware
Requirements,¡¨ VLSI-DAT, Hsinchu, April 2014.
75.
Che-Yu Wu, Y.S. Hsu,
C.T. Chiu, ¡§Object Recognition using Bag of words with Kernels for Big Data,¡¨ IEEE International Conference on Consumer Electronics, Taiwan, May
2014.
76.
Y. T. Yang, and C.T.Chiu, ¡§Boosted
Multi-class Object Detection with Parallel Hardware Implementation for
Real-Time Applications,¡¨ IEEE ICASSP, Italy, May, 2014.
77.
P.C. Chiu, Y.S. Hsu, C.T. Chiu, ¡§Analysis
of Cluster Ring Controller/Area Network for Enhanced Transmission and Fault-Tolerance
Capability on Vehicle Networks,¡¨ Advanced Microsystems for Automotive Applications, Berlin, Germany,
June 2014.
78.
Y. T. Yang, C.C. Liao, C. T. Chiu, ¡§Study of Efficient
Multiple Object Detection and Hardware Implementation,¡¨ VLSI/CAD Symposium,
Taiwan, Aug. 2014.
79.
T. T. Chu, C. T. Chiu, ¡§Fingerprint Recognition Based on
Minutiae Alignment,¡¨ IPPR conference on computer vision, graphics and image
processing, Taiwan, Aug. 2014.
80.
L.Y. Kuo and C.T. Chiu, ¡§Gradient-Based
Image Up-Scaling With Local Self Similarity¡¨ IEEE GlobalSIP,
USA, 2014.
81.
J.W. Wang, T.H. Wang, C. T. Chiu, ¡§Edge-based
Motion and Intensity Prediction for Video Super-Resolution, IEEE GlobalSIP, USA, 2014.
•Technical Reports
•Patent